1. Field of the Invention
The present invention relates generally to semiconductor memory structures, e.g., SRAM, and particularly, an SRAM cell structure, array architecture and method of operation which provides a real-time adaptive tradeoff between immunity to single event upset (SEU) due to ionizing particles (including proton, neutron, pion, alpha particle, or heavy ions) and performance.
2. Description of the Prior Art
In single event upsets (SEU) due to ionizing events caused by comic rays, particles from terrestrial sources, and materials in proximity to the chip present a reliability challenge to semiconductor memories (e.g. SRAM, DRAM) and logic circuits. High performance SRAM sensitivity to cosmic rays—measured on the basis of fails per bit—has dropped by about 10× over the last 15 years, while the bits/chip has increased 1000×; hence the net fail rate per chip has increased about 100 times. Modern CMOS chips are increasingly more sensitive to neutrons below 100 MeV.
The approach taken by the industry to provide acceptable immunity to SEU has been overkill in design. For example, bulk CMOS SRAM cells having higher than necessary internal node capacitance, overly conservative beta ratio, higher than necessary supply voltage and well back bias are commonly employed, solely for the purpose of SEU concerns. The price for this conservative design is compromised performance, specifically, array access times. Once designed, the SEU exposure of these SRAM is frozen.
Currently, no structure or teaching in the art has been found which suggests the use of an SRAM sensing sub-array for accelerated collection of fail rate data for determining the operating point for optimum tradeoff between single event upset immunity and performance of a primary SRAM array, and providing real-time adaptive control of the operating conditions of the primary SRAM array.
Prior art teachings exist that, in part, teach the adjustment of various SRAM cell operating voltages to alter the sensitivity to SEU. For instance, the reference entitled “Proton-Sensitive Custom SRAM Detector”, by G. A. Soli, et al, IEEE Nuclear Science Symposium and Medical Imaging Conference, 1991, pp. 1541-1545, vol. 3, teaches a specially designed SRAM cell used as a proton sensor as shown in FIG. 1. The SRAM cell 10 shown in FIG. 1 includes a first inverter tied to a normal supply Vdd (=5V), while the second inverter is tied to a tunable voltage level Vo. The cell is initially loaded with a “low state” at node V1 and a “high state” at node V2. Due to the existing off-set, the cell is susceptible to be upset by heavy ion events. There are at least three disadvantages of this design: (1) The cell is inherently unbalanced; even when Vo=Vdd, the cell is still not fully balanced since two inverters are connected to two different power supplies. (2) This SRAM array can only be used as a particle monitor and cannot be used in normal operation with high reliability. (3) Since the cell has a built-in off-set, it is vulnerable to other types of errors such as read and/or write disturbances. Therefore, it would be difficult to distinguish whether the bit error is caused by radiation induced soft-error or other types of error mechanism.
U.S. Pat. No. 6,785,169 directed to memory cell error recovery, describes how the soft error rate in a semiconductor memory is improved via the use of a circuit and arrangement adapted to use a mirror bit to recover from a soft error. According to this reference, a semiconductor device includes first and mirror memory cells configured and arranged to receive and store a same bit in response to a write operation, with the memory cells more susceptible to a bit error in which the stored bit changes from a first state to a second state than to a change from the second state into the first state. The memory cells are separated by a distance that is sufficient to make the likelihood of both memory cells being upset by a same source very low. For a read operation, the bits stored at the first and second memory cells are compared. If the bits are the same, the bit from the first and/or mirror bit is read out, and if the bits are different, a bit corresponding to the more susceptible state is read out. In this manner, soft errors can be overcome. While using two identical arrays to catch and correct soft error is advantageous, it provides no means for speeding up error rate detection.
U.S. Pat. No. 6,583,470 directed to radiation tolerant back biased CMOS VLSI, describes a CMOS circuit formed in a semiconductor substrate having improved immunity to total ionizing dose radiation, improved immunity to radiation induced latch up, and improved immunity to a single event upset. However, this reference provides no means for improving the reliability of memory arrays by determining the actual SEU exposure to a given radiation environment; rather, the focus of this device is to boost the immunity to radiation induced upset on CMOS logic circuits.
U.S. Pat. No. 4,983,843 directed to a radon gas detector instrument comprising: a filter for trapping alpha radon daughters of said gas, an air pump for drawing ambient air through the filter, a DRAM devoid of an alpha particle barrier layer, located adjacent the filter, for exposure to alpha particles trapped by the filter, apparatus for cyclically relaxing all cells of the DRAM, waiting for a significant period of time for cells of the DRAM to become charged by said alpha particles, then reading the DRAM to determine the number of charged cells in the DRAM, a display connected to the relaxing, waiting and reading means for displaying a count of the number of charged cells in units correlated to the intensity of radon gas in the ambient air. This reference is silent as to methods for accelerating SER and it would take significant period of time to collect the information.
Accordingly there is a need to provide a novel system and method for automatically adjusting one or more electrical parameters in memory, e.g., SRAM arrays, and more particularly, a novel system and method for setting the SEU sensitivity of a primary SRAM memory array to a predetermined fail rate in an ionizing particle environment.
It would thus be highly desirable to provide a novel memory structure, e.g., SRAM array, that enables combinations of the beta ratio, N-well bias, and the power supply of the cell to be dynamically adjusted to assure immunity to upsets of the internal latched state of the SRAM cells caused by an ionizing particles, while maximizing the cell performance.